PHASE LOCKED LOOP

1.0	Abstract

2.0	Introduction
		2.1	Objective
		2.2	Background

3.0	Theory
		3.1	The Circuit
		3.2	Operation Principals
		3.3	PLL Parameters


4.0	Procedure

5.0	Results and Observations

6.0	Comments and Conclusions
		6.1	General
		6.2	Questions
		6.3	Applications

7.0	Endnotes and References

1.0 Abstract:

Phase Locked Loop is an important circuit found in various communication devices, and here studied in a set up to synchronize input and local carrier signals for coherent demodulation of AM signals. PLL consists of a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector and loop filter combined produces an error signal which amplitude is linearly related to the phase difference of input and local carrier signals. The voltage-controlled oscillator adjusts appropriately to tune both signals as desired. PLL in integrated chip LM565C was studied and the working principals of PLL were verified. Parameters such as capture range, hold in range and loop gain were investigated. Capture range was determined to be 7.4 to 12.3 kHz, and the hold in range was found to be 4.8 to 14.6 kHz. PLL is an important and intricate circuit that can be studied at greater lengths.

2.0 Introduction:

2.1 Objective:

The aim was to determine and verify important parameters such as hold in range, capture range of a standard phase locked loop(PLL) integrated chip LM565C. In the process, the project also investigates PLL components, basic principals behind its operation and its general relevance in the communication devices.

2.2 Background:

In carrier suppressed or little carrier AM transmitted signals require a local carrier for synchronous demodulation. During the transmission the frequency and phase of the transmitted signal tend to get distorted due to noise or interference, and the signal carrier and receiver's local carrier tend to differ. A mechanism is required to ensure that the receiver's local carrier frequency and phase are same as that of the transmitted signals. Phase Locked Loop (PLL) facilitates or ensures that both transmitted and receiver carrier signals are in tune.

"A phase locked loop is a device, that can follow the frequency of its input signal and generates an output signal of the same frequency." The concept was in use since 1930 and various companies have developed integrated chips to implement the circuit; in this lab LM565 developed by National Semiconductor, Inc has been used. Moreover, Phase Locked Loop is a extensively used modern wireless communication device.

3.0 Theory:

3.1 The Circuit:

Figure I: The Block Diagram of PLL

A phase locked loop consists of three major parts: Phase Detector, Loop Filter and Voltage Controlled Oscillator (VCO). It is connected in a basic feedback-demodulator setup. The analysis of the circuit can be conducted at various levels, in this report only basic analysis is conducted and the electronic details are not provided.

3.2 Operation Principals:

Phase Detector is a just a multiplier which major function in the PLL is to produce a difference of input carrier signal and the local carrier signal. In other words, "multiplier is a function of the phase difference of the two input signals [CHARAN]". Mathematically, the relation can be illustrated as follows:

Loop Filter is there to block any unwanted signals such as the signals with frequency of twice the carrier frequency and any noise. It is a sharp low pass filter. The result after multiplication of local carrier signal and filtering is called the error signal or the control signal. Note that if the phase difference is zero (actually 90°) the error signal is zero [CHARAN]. Error signal is expressed as

An input voltage can control VCO frequency in a linear manner. In order to use this device to tune the two signals there must exist a linear relation between voltage to phase error. "The amplitude of the error signal is directly related to phase error [CHARAN]." Depending on the amount of error the VCO adjusts the local in attempting to match the reference or transmitted carrier signal.

3.3 PLL Parameters(Pre Lab Calculations):

When using a PLL IC, there are four parameters that most concern the user. They are free running frequency, hold in range, capture or pull in range, and loop gain. The free running frequency can be considered as the standard carrier signal. It is defined in the specification as fo = 0.3/RoCo. In this project the free running frequency was held to be 10 kHz.

Hold in range is the range of frequencies for which both signals will be in tune after being locked. It is defined in the specification as fH= 8fo/Vc where fo is the free running frequency and Vc is the total voltage to the circuit. In the project fH was calculated to be 5000Hz. The capture range is the range of frequencies for which the phase lock loop will lock. The capture range is defined as

Loop Gain is a multiplication of Ko and Kd, which produces a measure of "amount of phase change between the input and the VCO signal for a shift in input signal frequency." Ko is the oscillator sensitivity. The instantaneous frequency is related to the amplitude of the error signals (which is a voltage) as follows: winst = wcarrier + Koeo(t). Note that the frequency changes linearly in relation to error voltage applied. That is voltage controls the output frequency of the output.The other factor is Kd which phase detector sensitivity.

4.0 Procedure:

Figure2: The Block Diagram Setup for PLL Demodulation of PM signals

The circuit shown in Figure 2 was connected and the free running frequency was set to 10 Khz. Also, output of free running oscillator was taken and plotted in Graph I. The DC voltages at pins 6 and 7 were measured using the oscilloscope to be the same value of 6 volts.

Second, a signal of Vi(t)=1sin(2p x 4000t) was applied at pin 2. Initially, the phase locked loop was not locked and was not tracking. The frequency of the input signal was slowly increased and the lower edge capture range marked fc- was found. The phase difference between VCO output and input signal, and the voltage difference between Vd-Vref were measured at approximate integer multiple frequencies; until the fH+ or the upper edge of the tracking range was encountered. The results were summarized in Table

Third, the frequency was slowly decreased, and the upper edge fc+ of the capture range was noted. The frequency was further decreased and similar data as above was recorded in Table II. Moreover, the capacitor C2 was changed from 0.047 mf to 1.0 mf and the pull in range (fc-, fc+) and the hold range(fh-, fh+) were recorded in Table III.

5.0 Results and Observations:

The free running frequency was set at 10 kHz and the capture range was expected to fall close to it; and was found to be in the range of 7.4 kHz to 4.8 kHz.


The relation between instantaneous vilocity and Vd - Vref was plotted in Graph I. The VCO sensitivity was defined as Ko=2p/(slope). The slope was 0.0002 V/hz, thus Ko was determined to be 31415.9 (rad/sec V).



Another parameter of importance is the phase-detector sensitivity KD. It is defined as KD= (180/p)[slope] V/rad where the slope is that of phase difference vs Vd-Vref. The slope was 85.7 degrees/V, thus the phase-detector sensitivity was found to be 0.668 V/rad.


6.0 Comments and Conclusions:

6.1 General:

One can note that there exist a linear relation between the Vd-Vref and the phase difference between the transmitted carrier and local carrier or set signal. Graph III shows this linear relation.

According to device specifications the hold range was to be within 5 kHz after initially being locked. In the lab the input and local signals remained locked and in tune up to about 7kHz as fi was increased or decreased from initial lock. The deviation is significant and could not be explained in terms of component error range or noise.

To summarize, free running frequency, hold range and capture range are working parameters when employing PLL for general purposes. The capture range is close to the free running frequency. The loop gain provides a measure of how good a PLL can be. Obviously, the more sensitive the Ko and Kd the better the PLL

6.2 Questions:

Explain briefly why Vi(t) and Vo(t) are not synchronized during the time when the PLL is not in lock condition?

For PLL to track Vi(t) and Vo(t) two conditions must be met: first input and output frequency must be close enough to free-running frequency to acquire lock. Even after acquiring the lock the PLL will only tack for a finite range called hold in or lock range [LATHI98]. Obviously, if the PLL was not in the lock condition then Vi(t) and Vo(t) will not be synchronized.

How do the measure values of Kd and Ko compare with those in the spec's? Comment on any deviation.

From the specification LoopGain= KoKd=33.6 fo/Vc where fo is the free running frequency and Vc is the total voltage supply to the circuit. From the specification the loop gain was found to be KoKd= 33.6(10000)/16=21000 (1/sec), and from the lab the loop gain was found to be KoKd= 31416 x 0.668 = 20985 (1/sec). (Please note the specification sheet in Appendix for both formulas). The deviation was negligible, however any deviation could be explained in terms of error range of the external devices used, and noise in actual systems.

In step 8, when C2 was replaced by a 1mf capacitor, the PLL when out of sync. Why?

The free running frequency is defined as 0.3/RoCo where Co=C2. When the C2 was Changed from 0.047 mf to 1mf the free running frequency must have altered considerably. The alteration would have increased the difference between input signal and the free running frequency significantly such that it was no longer possible to be in lock or in lock range.

6.3 Applications:

bit synchronization

symbol synchronization

carrier tracking,

frequency multiplication and division

FM demodulation

motor speed controls

frequency synthesis

FSK decoders

space communications

7.0 Endnotes and References:

[LATHI98]
Lathi, B. P.,Modern Digital and Analog communication Systems.

Oxford Press, Toronto, Third Edition, 1998.


[CHARAN]
Charan, Langton. "Unlocking the Phase Lock Loop" www.complextoreal.com/pll.pdf

Online. Internet. 03 Apr. 2002.