-- Name1:		Natkeeran 
-- Name2:		Praba 
-- Project:		FIFO Buffer
-- File:		ele758/intro6/FIFO_Buffer4.vhd 
-- Revision:		Final
-- Data:		Oct/18/2002

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY FIFO_Buffer4 IS
PORT(
		DataIn		:	IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		LowWrtEn	:	IN STD_LOGIC;
		LowOutEn	:	IN STD_LOGIC;
		clk			:	IN STD_LOGIC;
		
		FullBuffer	:	OUT STD_LOGIC;
		EmptyBuffer	:	OUT STD_LOGIC;
		DataOut		:	OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		Temp		:   IN  STD_LOGIC_VECTOR(5 DOWNTO 0));
END FIFO_Buffer4;

ARCHITECTURE Description OF FIFO_Buffer4 IS

TYPE FIFO_Buff IS ARRAY(0 TO 5) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL FIFO_Array	:	FIFO_Buff;

SIGNAL Write_ptr	:	INTEGER RANGE 0 TO 5 := 0;
SIGNAL Read_ptr		:	INTEGER RANGE 0 TO 5 := 0;
SIGNAL TempFull		:	STD_LOGIC;
SIGNAL TempEmpty	:	STD_LOGIC;

SIGNAL Last_wrt		: 	STD_LOGIC;
SIGNAL Last_rd		:	STD_LOGIC;

BEGIN    
    -- FIFO_FULL Check and Set Process
	-- Set the "FullBuffer" condition
	-- Set the "FullBuffer"'s temporary signal "TempFull" 
	-- When both "Write_ptr" and "Read_ptr" equal and last action was a write.
	-- This happens at clock event low to let know the status to the read routine 	

PROCESS(clk, LowOutEn)
BEGIN
	IF (clk'event AND clk='0') THEN

		IF(LowOutEn='0') THEN
			TempFull <= '0';
		ELSE
			IF((Write_ptr = Read_ptr) AND (Last_wrt='1')) THEN
				TempFull <= '1';

			ELSIF ((Last_rd='1') AND (TempFull='1')) THEN
				TempFull <= '0';
			ELSIF(Last_wrt='1' AND Last_rd='1') THEN
				TempFull <= '0';
			ELSE
				TempFull <= '0';
			END IF;
		END IF;
	END IF;
END PROCESS;	

	-- Writing Process:
	-- write when clock event HIGH
	-- write when not full
	-- increment as 0 1 2 3 4 5 0 1 2 3 4 5 
	-- If Last_rd is high set low Last_wrt,
	-- overwrite Last_wrt as high if actually writing take place 

PROCESS(clk,LowWrtEn)
	BEGIN
	IF(clk'event AND clk='1') THEN
		
	IF(Last_rd='1') THEN
				Last_wrt <= '0';
	END IF;		

		IF((LowWrtEn = '0') AND (TempFull = '0')) THEN
	    		FIFO_Array(Write_ptr) <= DataIn;
				Last_wrt <= '1';
											
	    		IF (Write_ptr < 5)THEN
	    			Write_ptr <= Write_ptr + 1;
				ELSE
	    		    Write_ptr <= 0;
	    		END IF;						
    	END IF;
	END IF;
	END PROCESS;
	
	-- FIFO_EMPTY Check and Set Process 
	-- Set EmptyBuffer 
	-- If both pointers are equal and last action is a read then set high TempEmpty
	-- If you are writing, set TempEmpty low
	-- TempEmpty='0' for some other conditions as shown below  
	
	PROCESS(clk, LowWrtEn)
	BEGIN
		IF(clk'EVENT AND clk='1') THEN
				
			IF(LowWrtEn='0') THEN
				TempEmpty <= '0';
			ELSE
				IF((Write_ptr=Read_ptr) AND (Last_rd='1')) THEN
						TempEmpty <= '1';
				ELSIF((Last_wrt= '1')and (TempEmpty = '1')) THEN
					TempEmpty <= '0';								
				ELSIF(Last_wrt='1' AND Last_rd='1') THEN
					TempEmpty <= '0';
				ELSE
					TempEmpty <= '0';
				END IF;
			END IF;		
		END IF;
	END PROCESS;		

	-- Reading Process	                 
	-- Read when not empty
	-- empty when Write_ptr=Read_ptr
	-- increment as 0 1 2 3 4 5 0 1 2 3 4 5
	-- If Last_wrt is high set low Last_rd,
	-- overwrite Last_rd as high if actually reading take place 

	PROCESS(clk, LowOutEn)
	BEGIN
		IF(clk'event AND clk='0')THEN 

		IF(Last_wrt='1') THEN
				Last_rd <= '0';
		END IF;		

		IF(LowOutEn='0' AND TempEmpty='0')THEN		
				DataOut <= FIFO_Array(Read_ptr);
				Last_rd <= '1';						
	
				IF (Read_ptr < 5)THEN
					Read_ptr <= Read_ptr + 1;			
				ELSE
					Read_ptr <= 0;
				END IF;	
		ELSIF(LowOutEn='0' AND TempEmpty='1') THEN
				DataOut <= "11111111";		
		END IF;
		END IF;
	END PROCESS;  

FullBuffer <= TempFull;
EmptyBuffer <= TempEmpty;

END Description;